1. Field of the Invention
The invention relates to a method for fabricating an NMOS transistor.
2. Description of the Prior Art
Both theoretical and empirical studies have demonstrated that carrier mobility in a transistor can be greatly increased when a stress of sufficient magnitude is applied to the conduction channel of a transistor to create a strain therein. Stress is defined as force per unit area. Strain is a dimensionless quantity defined as the change in a particular dimension of an item: for example, the change in the item's length, versus the initial dimension of that item: for example, its original length, when a force is applied in the direction of that dimension of the item: for example, in the direction of the length of the item's length. Strain can be either tensile or compressive. In p-type metal oxide semiconductors (PMOS), the application of a compressive longitudinal stress, i.e. in the direction of the length of the conduction channel, creates a strain in the conduction channel which is known to increase the drive current of a PMOS transistor. However, if that same stress is applied to the conduction channel of an NMOS transistor, its drive current decreases.
It has been proposed to increase the performance of an NMOS and a PMOS by applying a tensile longitudinal stress to the conduction channel of an NMOS and applying a compressive longitudinal stress to the conduction channel of a PMOS. Such proposals have focused on masked processes involving the masking of a PMOS portion of the chip and altering the materials used in shallow trench isolation regions near the conduction channel of the PMOS to apply a desired stress thereto. Separate steps would then be performed to mask the NMOS portion of the chip and alter the materials used in shallow trench isolation regions near the conduction channels of the NMOS to apply a desired stress thereto. Other proposals have involved masked processed centered on modulating intrinsic stresses present in spacer features.
Silicon germanium is a desirable lattice-mismatched semiconductor for use in forming strained silicon transistor channels. A strain is created when a second semiconductor is grown onto a single-crystal of a first semiconductor when the two semiconductors are lattice-mismatched to each other.
Silicon germanium grows epitaxially on silicon having a crystal structure aligned with the silicon crystal structure. However, because silicon germanium normally has a larger crystal structure than silicon, the epitaxially grown silicon germanium becomes internally compressed, and results in improved hole mobility, which improves the performance of a PMOS transistor.
In other proposals using strained silicon, an epitaxial layer composed of silicon carbide is grown on the silicon substrate. Since silicon carbide has a smaller crystal structure than silicon, the epitaxially grown silicon carbide layer will produce a tensile strain on the silicon substrate. This results in improved electron mobility, which improves the performance of an NMOS transistor.
Please refer to FIGS. 1 through 5. FIGS. 1 through 5 illustrate a method for fabricating an NMOS transistor according to the prior art. As shown in FIG. 1, a substrate 10 having a gate structure 12 thereon is provided. The substrate 10 is preferably a wafer or a silicon on insulator (SOI) substrate, and the gate structure 12 is composed of a gate dielectric 14 and a gate 16. An offset spacer 18 is formed on the sidewall of the gate structure 12, and a shallow trench isolation 20 is formed surrounding the region outside the active area of the transistor.
As shown in FIG. 2, a pre-amorphorized implantation (PAI) process is performed thereafter with antimony (Sb) or germanium (Ge) to damage the silicon lattice of the substrate 10 for forming an amorphorized region 22 at two sides of the gate structure 12. Next, an etching process is performed by using the gate structure 12 as a mask to form a recess (not shown) at two sides of the gate structure 12 in the substrate 10, and a selective epitaxial growth (SEG) process is performed to form an epitaxial layer (not shown) composed of silicon carbide in the recess.
After the selective epitaxial growth process is completed, as shown in FIG. 3, an ion implantation process is performed to implant an n-type dopant into the substrate 10, and a rapid thermal annealing process is performed thereafter to form a lightly doped drain (LDD) 26 at two sides of the gate structure 12.
After the lightly doped drain 26 is formed, as shown in FIG. 4, a spacer 28 is formed on the sidewall of the gate structure 12. Subsequently, as shown in FIG. 5, another ion implantation process is performed to implant n-type dopant into the substrate 10 at two sides of the spacer 28 for forming a source/drain region 30, thus complete the fabrication of an NMOS transistor.
However, as noted above, a pre-amorphorized implantation process is performed prior to the selective epitaxial growth by injecting atoms such as antimony or germanium into the silicon substrate for damaging the lattice structure of the substrate. Since germanium or antimony used during the amorphorizing step is larger than silicon, these large atoms will often cause compensated stress for the carbon atoms deposited during the epitaxial growth process, thus producing an interstitial defect in the silicon substrate and inhibiting the formation of silicon carbide. The inhibition of silicon carbide ultimately reduces the tensile strain required for the NMOS transistor and thus reducing the performance of the transistor accordingly.